Caple C871i Uživatelský manuál stáhnout pdf (Strana 481)

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Apple II Computer Info

bit 7: This is set when an interrupt (IRQ) was generated by the SSC

$C0xA: Command register (read/write)

bit 0: Setting this bit turns on the Data Terminal Ready

bit 1: Setting this bit will cause an interrupt to be generated every time a

byte is received.

bits 2&3: Control the transmitter as follows:

bit 2 bit 3

0 0 transmit interrupt disabled, RTS high, transmitter off

0 1 transmit interrupt disabled, RTS low, transmitter on

1 0 transmit interrupt enabled, RTS low, transmitter on

1 1 transmit interrupt disabled, RTS low, transmit break

bit 4: If this bit is set, and bits 2 and 3 are both zero, all data received

will automatically be echoed back to the sender.

bits 5-7: If bit 5 is set, parity will be checked and transmitted besed on the

following settings of bits 6 & 7:

bit 6 bit 7

0 0 odd parity transmitted and checked

1 0 even parity transmitted and checked

0 1 mark transmitted, no check

1 1 space transmitted, no check

$C0xB: Control register

bits 0-3: Baud rate:

bit 3 bit 2 bit 1 bit 0

0 0 0 0 Use external clock

0 0 0 1 50 bps

0 0 1 0 75 bps

0 0 1 1 109.92 bps

0 1 0 0 134.58 bps

0 1 0 1 150 bps

0 1 1 0 300 bps

0 1 1 1 600 bps

1 0 0 0 1200 bps

1 0 0 1 1800 bps

1 0 1 0 2400 bps

1 0 1 1 3600 bps

1 1 0 0 4800 bps

1 1 0 1 7200 bps

1 1 1 0 9600 bps

1 1 1 1 19200 bps

bit 4: Receiver clock source. When set (1), use baud rate generator, when

clear (0), use external clock

bits 5-6: Word legnth:

bit 6 bit 5

0 0 8 bits

0 1 7 bits

1 0 6 bits

1 1 5 bits

bit 7: If clear, send one stop bit, if set, send two.

Final note: On the Apple SSC, $C0x1 and $C0x2 report the status of the DIP

switches on the card.

Newsgroups: comp.sys.apple2.programmer

Apple II Computer Technical Information : Apple II Family Hardware Info

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Caple C871i Uživatelský manuál Strana 481

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